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document # sram136 rev or revised july 2009 p4c1281/p4c1282 ultra high speed 64k x 4 cmos static rams features full cmos, 6t cell high speed (equal access and cycle times) C 12/15/20/25 ns (commercial) C 15/20/25/35 ns (industrial) C 20/25/35/45 ns (military) low power operation 5v 10% power supply separate inputs and outputs C p4c1281 input data at outputs during write C p4c1282 outputs in high z during write fully ttl compatible inputs and outputs standard pinout (jedec approved) C 28-pin 300 mil dip, soj C 28-pin 350 x 550 mil lcc functional block diagram pin config urations dip (p5, c5, d5-2), soj (j5) description the p4c1281 and p4c1282 are 262,144-bit (64kx4) ultra high-speed static rams similar to the p4c1258, but with separate data i/o pins. the p4c1281 features a transpar - ent write operation; the outputs of the p4c1282 are in high impedance during the write cycle. the rams operate from a single 5v 10% tolerance power supply. access times as fast as 12 nanoseconds are available, permitting greatly enhanced system operating speeds. cmos is used to reduce power consumption. the p4c1281 and p4c1282 are available in 28-pin 300 mil dip and soj, and a 28-pin 350x550 mil lcc providing excellent board level densities. lcc (l5)
p4c1281/p4c1282 - ultra high speed 64k x 4 cmos static rams page 2 document # sram136 rev or dc electrical characteristics (over recommended operating temperature & supply voltage) (2) sym parameter value unit v cc power supply pin with respect to gnd -0.5 to +7 v v term terminal voltage with respect to gnd (up to 7.0v) -0.5 to vcc + 0.5 v t a operating temperature -55 to +125 c t bias temperature under bias -55 to +125 c t stg storage temperature -65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma maximum r atings (1) recommen ded operating conditions grade (2) ambient temp gnd v cc commercial 0c to 70c 0v 5.0v 10% industrial -40c to +85c 0v 5.0v 10% military -55c to +125c 0v 5.0v 10% capacita nces (4) (v cc = 5.0v, t a = 25c, f = 1.0mhz) sym parameter conditions typ unit c in input capacitance v in =0v 8 pf c out output capacitance v out =0v 10 pf sym parameter test conditions p4c1281/1282 unit min max v ih input high voltage 2.2 v cc + 0.5 v v il input low voltage -0.5 (3) 0.8 v v hc cmos input high voltage v cc - 0.2 v cc + 0.5 v v lc cmos input low voltage -0.5 (3) 0.2 v v cd input clamp diode voltage v cc = min, i in = -18 ma -1.2 v v ol output low voltage (ttl load) i ol = +8 ma, v cc = min 0.4 v v oh output high voltage (ttl load) i oh = -4 ma, v cc = min 2.4 v i li input leakage current v cc = max, v in = gnd to v cc mil -10 +10 a ind/com -5 +5 i lo output leakage current v cc = max, ce = v ih , v out = gnd to v cc mil -10 +10 a ind/com -5 +5 i sb standby power supply current (ttl input levels) ce v ih , v cc = max, f = max, outputs open mil 40 ma ind/com 35 i sb1 standby power supply current (cmos input levels) ce v hc , v cc = max, f = 0, outputs open v in v lc or v in v hc mil 20 ma ind/com 15 n/a = not applicable
p4c1281/p4c1282 - ultra high speed 64k x 4 cmos static rams page 3 document # sram136 rev or power dissipatio n characteristics vs. speed sym parameter temperature range -12 -15 -20 -25 -35 -45 unit i cc dynamic operating current* commercial 170 160 155 150 n/a n/a ma industrial n/a 170 160 155 150 n/a ma military n/a n/a 160 155 150 145 ma * v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce = v il , oe = v ih . sym parameter -12 -15 -20 -25 -35 -45 unit min max min max min max min max min max min max t rc read cycle time 12 15 20 25 35 45 ns t aa address access time 12 15 20 25 35 45 ns t ac chip enable access time 12 15 20 25 35 45 ns t oh output hold from address change 2 2 2 2 2 2 ns t lz chip enable to output in low z 2 2 2 2 2 2 ns t hz chip disable to output in high z 7 8 10 10 15 15 ns t pu chip enable to power up time 0 0 0 0 0 0 ns t pd chip disable to power down 12 15 20 25 25 30 ns ac electrical characteristicsread cycle (v cc = 5v 10%, all temperature ranges) (2) timing waveform of read cycle no. 1 (address controlled) (5,6) timing waveform of read cycle no. 2 ( ce controlled) (5,7,8)
p4c1281/p4c1282 - ultra high speed 64k x 4 cmos static rams page 4 document # sram136 rev or notes: 1. stresses greater than those listed under maximum r atings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air fow. 3. transient inputs with v il and i il not more negative than C3.0v and C100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. 5. we is high for read cycle. 6. ce is low for read cycle. 7. address must be valid prior to, or coincident with ce transition low. 8. read cycle time is measured from the last valid address to the frst transitioning address. 9. transition is measured 200 mv from steady state voltage prior to change, with loading as specifed in figure 1. this parameter is sampled and not 100% tested. ac characteristicswrite cycle (v cc = 5v 10%, all temperature ranges) (2) sym parameter -12 -15 -20 -25 -35 -45 unit min max min max min max min max min max min max t wc write cycle time 12 13 15 20 30 40 ns t cw chip enable time to end of write 8 10 15 20 30 35 ns t aw address valid to end of write 8 10 15 20 25 35 ns t as address setup time 0 0 0 0 0 0 ns t wp write pulse width 9 10 15 20 25 35 ns t ah address hold time from end of write 0 0 0 0 0 0 ns t dw data valid to end of write 6 7 10 13 15 20 ns t dh data hold time 0 0 0 0 0 0 ns t wz write enable to output in high z 6 7 8 10 10 15 ns t ow output active from end of write 2 2 2 2 2 2 ns t awe write enable to data-out valid (p4c1281) 12 13 18 20 30 35 ns t adv data-in valid to data-out valid (p4c1281) 12 13 18 20 30 35 ns
p4c1281/p4c1282 - ultra high speed 64k x 4 cmos static rams page 5 document # sram136 rev or timing waveform of write cycle no. 1 ( we controlled) (10, 11, 12) notes: 10. ce and we must be low for write cycle. 11. if ce goes high simultaneously with we high, the output remains in a high impedance state 12. write cycle time is measured from the last valid address to the frst transitioning address. timing w aveform of write cycle no. 2 ( ce controlled) (10, 11, 12)
p4c1281/p4c1282 - ultra high speed 64k x 4 cmos static rams page 6 document # sram136 rev or ac test conditions truth table p4c1281 (p4c1282) input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 mode ce we i/o power standby h x high z standby read l h d out active write l l d in (high z) active figure 1. output load figure 2. thevenin equivalent * including scope and test fxture. note: because of the ultra-high speed of the p4c1281 and p4c1282, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fngers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal refections, proper termination must be used; for example, a 50? test environment should be terminated into a 50? load with 1.73v (thevenin voltage) at the comparator input, and a 116? resistor must be used in series with d out to match 166? (thevenin resistance).
p4c1281/p4c1282 - ultra high speed 64k x 4 cmos static rams page 7 document # sram136 rev or ordering in formation
p4c1281/p4c1282 - ultra high speed 64k x 4 cmos static rams page 8 document # sram136 rev or cerdip dual i n-lin e package sidebrazed dual i n-lin e package pkg # c5 # pins 28 (300 mil) symbol min max a - 0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.485 e 0.240 0.310 ea 0.300 bsc e 0.100 bsc l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 - pkg # d5-2 # pins 28 (300 mil) symbol min max a - 0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.485 e 0.240 0.310 ea 0.300 bsc e 0.100 bsc l 0.125 0.200 q 0.015 0.060 s1 0.005 - 0 15
p4c1281/p4c1282 - ultra high speed 64k x 4 cmos static rams page 9 document # sram136 rev or soj small outli n e ic package pkg # j5 # pins 28 (300 mil) symbol min max a 0.120 0.148 a1 0.078 - b 0.014 0.020 c 0.007 0.011 d 0.700 0.730 e 0.050 bsc e 0.292 0.300 e1 0.335 0.347 e2 0.262 0.272 q 0.025 - recta ng ular leadless chip carrier pkg # l5 # pins 28 symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.342 0.358 d1 0.200 bsc d2 0.100 bsc d3 - 0.358 e 0.540 0.560 e1 0.400 bsc e2 0.200 bsc e3 - 0.558 e 0.050 bsc h 0.040 ref j 0.020 ref l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd 5 ne 9
p4c1281/p4c1282 - ultra high speed 64k x 4 cmos static rams page 10 document # sram136 rev or plastic dual i n-lin e package pkg # p5 # pins 28 (300 mil) symbol min max a - 0.210 a1 - b 0.014 0.023 b2 0.045 0.070 c 0.008 0.014 d 1.345 1.400 e1 0.270 0.300 e 0.300 0.380 e 0.100 bsc eb - 0.430 l 0.115 0.150 0 15
p4c1281/p4c1282 - ultra high speed 64k x 4 cmos static rams page 11 document # sram136 rev or revisions document number sram136 document title p4c1281/p4c1282 - ultra high speed 64k x 4 cmos static rams rev issue date origin ator description of change or july 10, 2009 jdb new data sheet

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